RTL Power Analysis and Optimization

In this free, half-day workshop covering the fundamentals of power optimization—a critical component in today's chip design—you will expand your job prospects in the competitive and growing chip design industry.

We’ll discuss how to analyze, debug and optimize at RTL level—the principle abstraction used for defining electronic systems and the gold standard in design and verification. 

You’ll leave with a basic understanding of the different components of RTL power and be better prepared for the numerous  RTL-related open jobs in the San Francisco Bay area.

Topics

•     Inputs and outputs for a standard RTL level power tool
•     Understanding of early RTL level static checks towards power linting
•     Activity and power profiling for various applications
•     Average and time-based power analysis
•     Visibility of power across category and hierarchies using text and UI
•     Clock gating efficiency and related flavors
•     Exploration of flop level as well as architectural clock gating inefficiencies
•     Different power reduction techniques and related debugging
•     Power regression toward trend analysis

Who should attend?

•     Students of digital design, Verilog design, physical design, and timing closure courses
•     Experienced professionals working in the VLSI chip design space

Presenter

Arindam Mitra, director of application engineering at ANSYS, has more than a decade of experience in application engineering.

Workshop Details

•     Presentation, Discussion, & Q&A: 3 hours
•     Hands-on Lab Exercises: 1 hour 
•     This event is sponsored by the UCSC Silicon Valley Extension VLSI Engineering Program.

Visit us on LinkedIn: VLSI Chip Design Silicon Valley—UCSC Extension