Engineering 2 1156 High Street, Santa Cruz, California 95064

Non-volatile memory (NVM) technology presents a promising alternative to traditional DRAMs with its non-volatility and near-zero standby power consumption but faces challenges like limited write endurance and high energy consumption. This thesis addresses these challenges by integrating NVM technologies into the memory hierarchy through memory-aware software-level solutions, resulting in significant improvements in energy efficiency and write endurance. By evaluating real-world NVM devices and introducing Predict and Write (PNW) and E2-NVM techniques, we achieve up to 85% reduction in bit flips and 56% in cache lines, as well as up to 56% reduction in energy consumption. Additionally, the proposed Hamming Tree indexing structure demonstrates up to a 67.8% improvement in energy efficiency. Furthermore, the thesis explores the impact of memory-aware strategies on performance, energy consumption, and lifetime, revealing significant enhancements in device longevity, reduced power consumption, and improved system latency. The findings underscore the importance of recent advances in NVM storage and highlight the potential for integrating these strategies into existing and future data management systems. Through the introduction of advanced software solutions and memory-aware data structures, this thesis offers a comprehensive framework for enhancing the efficiency and longevity of NVM devices, paving the way for broader adoption of NVM technologies in future data management systems.

Event Host: Saeed Kargar, Ph.D. Candidate, Computer Science and Engineering

Advisors: Professor Faisal Nawab and Professor Chen Qian

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