We will talk briefly about how Cadence applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality.

We will then take a deep dive into Cadence Cerebrus, an AI-enabled chip design optimization tool that provides improved power, performance and area along with a 10x to 20x productivity boost by leveraging machine learning for synthesis, place, and route. 

NOTE: Attendees need to bring laptops to participate in the exercises.

Presenter

• Sajan Sahili, MSEE, Principal Product Engineer at Cadence Design Systems

  Sajan supports the Digital Signoff group products. She joined Cadence as an intern about eight years ago and is involved in customer engagements for Innovus. She works to debug design issues to achieve the best performance of chips and identifies enhancements needed for Cadence tools. She also works on Cerebrus enablement and has led many successful Cerebrus engagements for key customers achieving and exceeding power, area, and timing goals. In her personal life, she is the mother to a four-legged fur ball and likes to travel and read fiction.

Registration

• If you are a UC Santa Cruz student, you can register for this event through Handshake
• If you are a UCSC Silicon Valley Extension student, please register here.

Host

This event is sponsored by the VLSI Engineering certificate program at UCSC Silicon Valley Extension and is one of a series of VLSI workshops scheduled for 2023. 

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