Predicting Implementation PPA with Synopsys RTL Architect

Traditionally, RTL design has been handled separately from synthesis and implementation. This separation had led to an iterative, inefficient flow which has resulted in longer design cycles. In this workshop, we will talk about RTL Architect's ability to reduce iterations, and its unique capability to identify PPA bottlenecks in RTL.

This is a great workshop for logic designers, design-for-test professionals, verification engineers, and project leaders who want next-level training for career growth to meet the demands of top Silicon Valley employers.

Take-Aways

  • Understand the challenges at the physical implementation phase of the project, including floor planning, congestion, power, and timing.
  • Learn how RTL Architect helps designers identify PPA bottlenecks at the RTL design phase of the project.

NOTE: Attendees need to bring laptops to participate in the exercises.

Presenters

Registration

Sponsors

This event is co-sponsored by Synopsys and the VLSI Engineering certificate program at UCSC Silicon Valley Extension.

Thursday, May 25, 2023 at 9:00am to 12:30pm

Silicon Valley Campus, 2110, 2130
3175 Bowers Avenue, Santa Clara, CA 95054

Recent Activity

You're not going yet!

This event requires registration.