Various studies have established that control dependencies introduced by control instructions are a fundamental and the most limiting bottleneck to CPU performance. Wastage of fetch bandwidth in wide superscalar processors is a known issue. We use static basic block size and dynamic (fetch) block size between taken control instructions to show that for a fetch width of 16, nearly 40% of fetch width is wasted on average, It is possible to better utilize fetch width as well as improve IPC by predicting multiple taken branches in a clock cycle and collapsing/ merging the instructions from multiple such partially filled consecutive packets, . In this work, we propose SuperBP which is an accurate and efficient branch predictor that can provide accurate and timely predictions to better utilize fetch bandwidth in wide fetch width systems.

Event Host: Bhawandeep Singh, Ph.D. Student, Computer Science & Engineering

Advisor: Jose Renau